Help need for distributed Hardware Simulation

[n***@yahoo.co.in]

Hello guys,
I am EDA guy, looking at prospects of building an HDL simulator which
can use parallelism in real-world hardware designs to simulate them
very fast on some dedicated hardware. Before reading further, please
know that my experience has solely been with EDA emulators and
simulators, and some of what I say might sound like crap to your
seasoned Parallel Computing guys.

The hardware of my choice would not be a supercomputer, but (I don't
know if such a thing exists), maybe a PCI slot card, with ten general
purpose processors, having their own local memories that they can
access very fast. These memories would be used as "scratch-pads" by the
processors, and the relevant data from these "scrath-pad" memory would
be updated to the main memory.
The central processor (the "main" processor of the workstation/desktop
computer) would run a simulation kernel, and schedule the threads on
the processors on the board.

Now my question is, does something like that exist? If it doesn't, what
comes closest to my requirement.

Guys, any help would be appreciated. I know, my question seems like a
utopic vision of something I desperately want. Please give me all the
help you can.

-Niraj

[Renato Golin]

Post by n***@yahoo.co.in
Now my question is, does something like that exist? If it doesn't, what
comes closest to my requirement.

Never heard of such thing, but the closest thing I know you can get is a
NVidia SLI (where you can theoretically put 4 GPUs on a single motherboard).

http://www.slizone.com/content/slizone/clubsli.html

Why don't you build a beowulf cluster ? It's cheaper and easier.

--renato

[c***@yahoo.com]

Post by n***@yahoo.co.in
The hardware of my choice would not be a supercomputer, but (I don't
know if such a thing exists), maybe a PCI slot card, with ten general
purpose processors, having their own local memories that they can
access very fast. These memories would be used as "scratch-pads" by the
processors, and the relevant data from these "scrath-pad" memory would
be updated to the main memory.
The central processor (the "main" processor of the workstation/desktop
computer) would run a simulation kernel, and schedule the threads on
the processors on the board.
Now my question is, does something like that exist? If it doesn't, what
comes closest to my requirement.

Sounds like a mircoway gigacube --something like 4 or 5 cards with
four each i860 or i960s in an x86 box. Microway doesn't build them anymore
but they had custom compilers etc. for it. Did a gigaflop when that was
still in the supercomputer range. They build Beowulfs now but might be a
help if this is a commercial venture:

www.microway.com

If you intend to do HDL stuff cards with multiple FPGAs might do the
trick, just realize the switching matrix in logic too. --use the main
system to program the FPGAs to emulate the particular target. Or maybe a
"typical" target or a selection of targets to verify target independence.

Please know I am in the "reading about them stage" with programmable logic
so some of what I say might sound like crap to your seasoned HDL guys :-)

3ch

[Scott Lurndal]

Post by n***@yahoo.co.in
Hello guys,
I am EDA guy, looking at prospects of building an HDL simulator which
can use parallelism in real-world hardware designs to simulate them
very fast on some dedicated hardware. Before reading further, please
know that my experience has solely been with EDA emulators and
simulators, and some of what I say might sound like crap to your
seasoned Parallel Computing guys.
The hardware of my choice would not be a supercomputer, but (I don't
know if such a thing exists), maybe a PCI slot card, with ten general
purpose processors, having their own local memories that they can
access very fast. These memories would be used as "scratch-pads" by the
processors, and the relevant data from these "scrath-pad" memory would
be updated to the main memory.
The central processor (the "main" processor of the workstation/desktop
computer) would run a simulation kernel, and schedule the threads on
the processors on the board.
Now my question is, does something like that exist? If it doesn't, what
comes closest to my requirement.
Guys, any help would be appreciated. I know, my question seems like a
utopic vision of something I desperately want. Please give me all the
help you can.
-Niraj

Maybe the Azul board, if you're willing to write in Java.

scott

[russell kym horsell]

Post by Scott Lurndal

Post by n***@yahoo.co.in
Hello guys,

[...]

Post by Scott Lurndal

Post by n***@yahoo.co.in
Now my question is, does something like that exist? If it doesn't, what
comes closest to my requirement.

[...]

Post by Scott Lurndal
Maybe the Azul board, if you're willing to write in Java.

[...]


Don't know much about Vega stuff, but a general-purpose multi mobo with
dual-core x86's is a simple way to go.
It's likely to run a bit cheaper and trouble-free than the a 10-slot
multi OP the was talking about.
S/W extensive and all free and well-tested.
Sure it will run hot like a furnace,
but linux SMP is pretty easy to work in and it's only for a year.
The novelty aspect will come from the n-way shared event list accessing. :)